Strained silicon is increasingly being used to improve the performance of silicon-based CMOS transistors. For example, tensile-strained silicon is one of the most promising solutions to improve Ion/Ioff ratio and transconductance when traditional devices reach physical size limits. Strained silicon is also attractive for use in semiconductor-based devices because of strained silicon's ability to be readily integrated into CMOS processes, standard MOSFET architectures, and circuit layouts.
For example, strained silicon enables improvements in CMOS performance and functionality via replacement of the bulk, cubic-crystal silicon with a tetragonally distorted, biaxially strained silicon surface thin film. In addition, strained silicon film has electronic properties that are superior to those of bulk silicon. For instance, the strained silicon film has greater electron and hole mobilities, which translate into greater drive current capabilities for NMOS and PMOS transistors.
Strained silicon has generally been formed using a strained silicon heterostructure that involves several steps. First a SiGe relaxed graded layer is formed to engineer the lattice constant of the SiGe alloy. The relaxed SiGe graded layer is an epitaxially-grown thin film with a sequence of layers that have a gradually increasing Ge content up to a final Ge composition. Next, a constant composition Ge film is grown to spatially separate the subsequent strained silicon film from the misfit dislocations that are intentionally introduced in the SiGe relaxed graded layer. The final step is the deposition of the silicon film, which is placed in a state of biaxial tension as it conforms to the lattice of the constant-composition SiGe layer.
Strained silicon has also been used in conjunction with silicon-on-insulator (SOI) devices. For example, B. Ghyselen et al. disclose a process of engineering strained silicon on insulator wafers using SMART CUT process. See B. Ghyselen et al., Engineering Strained Silicon on Insulator Wafers with the SMART CUT Technology, Solid-State Electronics 48, pp. 1285-1296 (2004). The contents of the above-identified publication is incorporated by reference as if set forth fully herein.
According to one process, tensile-strained silicon is formed on insulator wafers by starting with an epitaxial layer stack ending with relaxed SiGe on top of an intermediate graded buffer layer. Hydrogen implantation is then performed on the relaxed SiGe layer, and the SMART CUT process is used to peel off the very top part of the epitaxial stack and is transferred to another silicon substrate. A strained silicon layer is then grown on top of the relaxed SiGe layer (SGOI).
In another method, tensile-strained silicon is grown directly on the relaxed SiGe layer of the donor wafer. A bi-layer containing the strained silicon and the relaxed SiGe layer is then transferred to another substrate using the SMART CUT process. After removal of the SiGe layer, the tensile-strained silicon layer is exposed, forming strained silicon on insulator (sSOI).
While methods are know for growing strained silicon layers, there is a need for a method or process for creating strained silicon that is substantially or completely free of dislocations. Conventional methods of forming strained silicon such as use of a compositionally graded SiGe buffer layer or oxidation of SiGe produces threading dislocations in the resulting strained silicon layer. Even in the methods disclosed in the B. Ghyselen et al., dislocations in the SiGe layer are transferred or otherwise communicated to the adjacent strained silicon layer. Dislocations that are formed in strained silicon (particularly threading dislocations), however, impair the overall performance of the device.